The present invention relates generally to the field of electronic data processing and in particular to a system and method of high performance bus arbitration.
The transfer of data between functional units is a common operation of computer systems. Transferring a program from disk to memory to a processor; sending data from a graphics engine to a frame buffer to a video card; and sending input from a keyboard or mouse to a processor are all common examples of data transfer within a computer system.
FIG. 1 depicts a simplified diagram of a system bus architecture, indicated generally by the numeral 10. A system bus 12, which may be divided into an address channel, data channel, control channel and the like, interconnects system units. Master devices, such as the CPU 14 or a DMA engine 16, initiate data transfers across the bus 12—referred to herein as bus transactions—to or from slave devices, such as memory 18 and input/output circuits 20. When two or more independent masters 14, 16 are connected to the bus 12, their access to the bus is controlled by an arbiter 22.
As known in the art, one or more master devices 14, 16 assert a bus request to the arbiter 22. The arbiter 22 monitors activity on the bus 12, and when the bus 12 becomes available, sends a bus grant to one of the requesting master devices 14, 16. The granted master device 14, 16 may then initiate transactions across the bus 12, such as read or write cycles directed to one or more slave devices 18, 20.
While the system bus 10 works well for connecting a few master devices 14, 16 with a variety of slave devices 18, 20, it imposes a limitation that only one master device 14, 16 can access a slave device 18, 20 at one time. In high performance processors, it is often the case that two or more master devices 14, 16 may wish to independently access one or more slave devices 18, 20.
FIG. 2 depicts a high performance data transfer system, indicated generally by the numeral 30. A switch matrix 32, also known as a crossbar switch, interconnects a plurality of master devices 34 to a plurality of slave devices 36, in the most general case with any master device having access to any slave device. For example, FIG. 2 depicts Master 1 accessing Slave 1, and simultaneously, Master 2 accessing Slave 0. In some implementations, one or more of the slave devices 36 may include two or more address busses, allowing simultaneous access by more than one master device 34.
For a bus system 30 comprising n master devices 34 and a single slave device 36, only one arbiter is necessary within the switch matrix 32 to arbitrate competing accesses to the slave device 36. For an n×m crossbar system 30, with n masters 34 and m slaves 36, from one to m arbiters may be implemented. The highest performance will be achieved with m arbiters, with each arbiter dedicated to a slave device 36. With fewer than m arbiters—that is, with at least one arbiter performing arbitration for two or more slave devices 36—performance will degrade, as each arbiter can only arbitrate for one slave device 36 at a time, or within any given bus cycle. However, instantiating many arbiters consumes chip area, complicates routing, and increases power consumption.